a. The Field of the Invention
This invention relates to the field of integrated circuit manufacturing. In particular, the invention relates to concepts and implementation techniques for the quick and efficient design, correction and verification of masks utilized in the manufacture of integrated circuits.
b. Description of Related Art
In designing an integrated circuit (IC), engineers typically rely upon computer simulation tools to help create a circuit schematic design consisting of individual devices coupled together to perform a certain function. To actually fabricate this circuit in a semiconductor substrate the circuit must be translated into a physical representation, or layout, which itself can then be transferred onto the silicon surface. Again, computer aided design (CAD) tools assist layout designers in the task of translating the discrete circuit elements into shapes which will embody the devices themselves in the completed IC. These shapes make up the individual components of the circuit, such as gate electrodes, field oxidation regions, diffusion regions, metal interconnections, and so on.
The software programs employed by these CAD systems are usually structured to function under a set of predetermined design rules in order to produce a functional circuit. Often, these rules are determined by certain processing and design limitations. For example, design rules may define the space tolerance between devices or interconnect lines so as to ensure that the devices or lines do not interact with one another in any unwanted manner. Design rule limitations are frequently referred to as critical dimensions. A critical dimension of a circuit is commonly defined as the smallest width of a line or the smallest space between two lines. Consequently, the critical dimension determines the overall size and density of the IC. In present IC technology, the smallest critical dimension for state-of-the-art circuits is approximately 0.25 microns for line widths and spacings.
Once the layout of the circuit has been created, the next step to manufacturing the integrated circuit (IC) is to transfer the layout onto a semiconductor substrate. Optical lithography is a well known process for transferring geometric shapes onto the surface of a silicon wafer. The optical lithography process generally begins with the formation of a photoresist layer on the top surface of a semiconductor wafer. A mask having fully light non-transmissive opaque regions, which are usually formed of chrome, and fully light transmissive clear regions, which are usually formed of quartz, is then positioned over the photoresist coated wafer. Light is then shone on the mask via a visible light source or an ultra-violet light source. The light is focused to generate a reduced mask image on the wafer typically using an optical lens system which contains one or several lenses, filters, and or mirrors. This light passes through the clear regions of the mask to expose the underlying photoresist layer, and is blocked by the opaque regions of the mask, leaving that underlying portion of the photoresist layer unexposed. The exposed photoresist layer is then developed, typically through chemical removal of the exposed/non-exposed regions of the photoresist layer. The end result is a semiconductor wafer coated with a photoresist layer exhibiting a desired pattern which defines the geometries, features, lines and shapes of that layer. This pattern can then be used for etching underlying regions of the wafer.
Besides the aforementioned design rules, the resolution value of the exposure tool used in optical lithography also places limits on the designers of integrated circuit layouts. The resolution for an exposure tool is defined as the minimum feature that the exposure tool can repeatedly expose onto the wafer. Currently, the resolution for most advanced optical exposure tools is around 0.25 micron. As the critical dimensions of the layout become smaller and approach the resolution value of the lithography equipment, the consistency between the mask and the actual layout pattern developed in the photoresist is significantly reduced. Specifically, it is observed that differences in pattern development of circuit features depends upon the proximity of the features to one another.
With these limitations on IC design in mind, we note the data describing an IC pattern is usually represented in a condensed hierarchical fashion such as in a GDS-II data file. At the higher levels of pattern representation hierarchy, features are represented in a conceptual manner. For instance, a memory array may be described as having a given cell repeated for a certain number of rows and columns. The next lower level in the hierarchy might describe the basic memory cell, comprised of subcells A and B. Finally, at the lowest level, the most primitive subcells contain geometric primitives-rectangles and polygons. In order to generate a physical mask, the hierarchical data must first be flattened, enumerating every geometric instance described in the hierarchy. Flattening of the hierarchy typically results in several orders of magnitude increase in the size of data storage required to represent the pattern.
Since flattening the hierarchy results in such a large increase in the size of the file representing a given IC design, it is desirable to flatten the hierarchy at the latest point in the manufacture of a mask, which, in the best case, is at the time the mask design is loaded into the EB machine prior to physical manufacture. Currently however, this flattening process takes place at an earlier stage in the production of masks for some complicated IC""s. This is because the original mask design for a complicated IC is typically manipulated after the original design is completed in order to perform one of a number of operations on the design. These operations are performed because of the precision needed in the masks for complicated IC""s as the critical dimensions of these IC""s approach the resolution limits of optical lithography. Currently, these operations require some sort of flattening of the original design data in order to be performedxe2x80x94resulting in an earlier than desired flattening of the design data.
These operations include the performance of logical operations, the generation of optical proximity corrections, the generation of phase shifting masks, and the design rule checking of masks that have undergone these operations. For instance, since the physical mask making process may introduce known distortions in the mask that are dependent upon the particular EB machine being used, mask makers may use logical operations such as AND or NOT operations between design layers to generate new mask layers which compensate for these known distortions. Further, mask designers may generate sub-resolution optical proximity correction features for a mask to compensate for the proximity effects which occur when very closely spaced pattern features are lithographically transferred to a resist layer on a wafer. Similarly, mask designers may generate phase shifting masks to overcome the effect of resolution limits on achievable circuit critical dimensions. Currently, each of these operations requires a flattening of the original design data in order to be performed. Further, and more importantly, because they do not maintain the original true hierarchical data format of the mask design, it is extremely difficult and time consuming to verify currently known masks upon which one of the previously mentioned operations has been performed using conventional verification tools which require the same hierarchical data format as the original mask.
Therefore, what is desired is a method and apparatus for performing operations on integrated circuit mask designs that solve the aforementioned problems of currently existing systems.
As discussed above, currently known systems for performing operations on integrated circuit design layouts are not capable of preserving the original hierarchy of the design. This leads to several problems including a large increase in data, a reduction in processing speed, and the loss of the ability to quickly check processed designs for correctness using conventional verification tools.
Accordingly, the present invention solves the aforementioned problems by providing a method and apparatus for performing an operation in accordance with a particular set of operating criteria on a hierarchically described integrated circuit layout such that the original hierarchy of the layout is maintained.
Thus in one embodiment of the present invention, in a system for performing an operation on a hierarchically described photolithography mask containing a plurality of cells, a computer program product is provided which includes a first program data. The first program data includes hierarchically configured correction data corresponding to the hierarchically described layout such that if the first program data were applied to the flattened layout an output comprising data representative of the result of performing the operation on the layout would be generated.
In one embodiment, the first program data is further characterized in that it comprises a plurality of delta planes that correspond to the plurality of cells. In this instance, the delta plane of a particular cell comprises data representative of the difference between a correction plane of the particular cell and the delta planes corresponding to the children cells of the particular cell. Further, the correction plane for each cell of the plurality of cells comprises data that would generate an output representative of the result of performing the operation on the cell if the correction plane were applied to the flattened cell data.
In one embodiment, the delta plane for each cell in the hierarchically described integrated circuit layout accounts for interaction between each of the cell""s child cells and interaction between the cell""s primitive geometry and each of the cell""s child cells.
In a further characterization of the above embodiment the first program data may comprise a set of arithmetically or logically described delta planes. Still further, the first program data may be described by a GDS-II data file.
The present invention as summarized above with respect to a first program data may be alternatively characterized as a method of performing an operation on a hierarchically described integrated circuit layout. The method includes, in one embodiment, providing a hierarchically described layout as a first input wherein the layout comprises a plurality of cells, and providing a particular set of operating criteria as a second input. The method also includes performing a layout operation in accordance with the particular set of operating criteria on the layout and generating a first program data comprising hierarchically configured correction data corresponding to the hierarchically described layout. The first program data is generated in response to the layout operation such that if the first program data were applied to the flattened layout an output comprising data representative of the result of performing the operation on the layout would be generated.
In another embodiment of the method, the first program data comprises a plurality of delta planes that correspond to the plurality of cells. In this embodiment, the delta plane of a particular cell comprises data representative of the difference between a correction plane of the particular cell and the delta planes corresponding to the children cells of the particular cell. Further, the correction plane for each cell of the plurality of cells comprises data that would generate an output representative of the result of performing the operation on the cell if the correction plane were applied to the flattened cell data. Still further, in one embodiment, the delta plane for each cell in the hierarchically described integrated circuit layout accounts for interaction between each of the cell""s child cells and interaction between the cell""s primitive geometry and each of the cell""s child cells.
In another embodiment wherein the first program data is characterized as comprising a plurality of delta planes corresponding to the plurality of cells, the step of generating the first program data further comprises compiling and linking the hierarchically described layout. In this instance, compiling comprises generating a first correction layer for each cell in response to the particular set of operating criteria. Linking comprises modifying the correction layer of each cell in response to the particular set of operating criteria to generate the delta plane for each cell. In this instance, the delta plane of each cell accounts for interaction between each of the cell""s child cells and interaction between the cell""s primitive geometry and each of the cell""s child cells.
In a further characterization of this embodiment, for each cell in the layout the sum of the cell""s delta plane and the delta planes of the cell""s child cells comprises a correction plane of the cell. The correction plane for each cell in the plurality of cells comprises data that would generate an output data representative of the result of performing the operation on the cell if the correction plane were applied to the flattened cell data. In a further instance of the above embodiment, compiling and linking each comprise a depth-wise traversing of the integrated circuit layout.
In another embodiment of the method, linking and compiling may further comprise determining whether each cell has been previously defined and generating a first correction layer and delta plane comprising data indicative of a location of a first instance of a cell definition for each cell which has been previously defined.
A still further embodiment of the method includes combining the first program data with the data describing the integrated circuit layout to produce a second program data that describes a first corrected layout. The second program data is then provided to a design rule checker apparatus, and the design rule checker apparatus is operated to determine whether the first corrected layout falls within a set of integrated circuit design rules.
Another embodiment of the invention is characterized as a photolithography mask produced in accordance with the method steps summarized above.
Lastly, the method steps of the above embodiments may in one instance be performed by a computer running a program of instructions which implements these steps wherein the program is stored on any appropriate computer storage media such as a hard disk or server.
The present invention as summarized above with respect to a first program data and a method may also be alternatively characterized as an apparatus for performing an operation on a hierarchically described integrated circuit layout. The apparatus includes, in one embodiment, a resource for receiving hierarchically described layout as a first input wherein the layout comprises a plurality of cells, and a resource for receiving a particular set of operating criteria as a second input. The apparatus also includes an operation engine which performs a layout operation in accordance with the particular set of operating criteria on the hierarchically described layout, and a hierarchy preserver which generates a first program data comprising hierarchically configured correction data corresponding to the hierarchically described layout. The first program data is generated in response to the layout operation such that if the first program data were applied to the flattened layout an output comprising data representative of the result of performing the mask operation on the layout would be generated.
In another embodiment of the apparatus, the first program data comprises a plurality of delta planes that correspond to the plurality of cells. In this embodiment, the delta plane of a particular cell comprises data representative of the difference between a correction plane of the particular cell and the delta planes corresponding to the children cells of the particular cell. Further, the correction plane for each cell of the plurality of cells comprises data that would generate an output representative of the result of performing the operation on the cell if the correction plane were applied to the flattened cell data. Still further, in one embodiment, the delta plane for each cell in the hierarchically described integrated circuit layout accounts for interaction between each of the cell""s child cells and interaction between the cell""s primitive geometry and each of the cell""s child cells.
In another instance, the apparatus may also include a compiler and a linker. The compiler generates a first correction layer for each cell in response to the particular set of operating criteria. The linker modifies the correction layer of each cell in response to the particular set of operating criteria to generate the delta plane for each cell. In this instance, the delta plane of each cell accounts for interaction between each of the cell""s child cells and interaction between the cell""s primitive geometry and each of the cell""s child cells.
In a further characterization of this embodiment, for each cell in the layout the sum of the cell""s delta plane and the delta planes of the cell""s child cells comprises a correction plane of the cell. The correction plane for each cell in the plurality of cells comprises data that would generate an output data representative of the result of performing the operation on the cell if the correction plane were applied to the flattened cell data. In a further instance of the above embodiment, the compiler and the linker each perform a depth-wise traversing of the integrated circuit layout to generate the correction planes and delta planes respectively.
A still further embodiment of the apparatus includes a resource for combining the first program data with the data describing the integrated circuit layout to produce a second program data that describes a first corrected layout. A design rule checker is provided to give an indication as to whether the first corrected layout falls within a set of integrated circuit design rules.
In another embodiment of the apparatus, the compiler and the linker may operate to determine whether each cell has been previously defined and to generate a first correction layer and delta plane comprising data indicative of a location of a first instance of a cell definition for each cell which has been previously defined.
Lastly, the apparatus of the above embodiments may in one instance be characterized as a computer program product comprising a computer readable medium having a computer readable program code embodied therein for causing a computer to perform an operation on a hierarchically described integrated circuit layout such that the original hierarchy of the layout is maintained.
Each of the aforementioned embodiments of the present invention can be further characterized further by the following additional descriptions. For instance, the delta planes of the first program data may include either arithmetically or logically described data. Still further, the operation performed on the layout may include any logical or arithmetic operation including for instance, OPC corrections and logical operations such as AND, NOT, OR, NOR and NAND.
Similarly, the first program data may be in any hierarchical data format such as GDS-II, and the computer readable media may include any suitable media for the storage of either data files or program files such as a hard disk drive or a server. Lastly, each of the above embodiments of the present invention may be applied to any layout including bright-field, dark-field, and phase shifting layouts.
Other aspects and advantages of the present invention can be seen upon review of the figures, the detailed description and the claims which follow.